4501_M Datasheet, PDF (113/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
HARDWARE
INSTRUCTIONS
Skip condition
Datailed description
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– In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to reg-
ister B, and the low-order 4 bits (AD3–AD0) of comparator register to register A.
(Q13: bit 3 of A/D control register Q1)
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– Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
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V22 = 0: (ADF) = 1
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(P) = 1
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(WDF1) = 1
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– In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
– Transfers the contents of A/D control register Q1 to register A.
– Transfers the contents of register A to A/D control register Q1.
– Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
– When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)
– No operation; Adds 1 to program counter value, and others remain unchanged.
– Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruc-
tion. However, the voltage drop detection circuit is valid.
– Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
Operations of all functions are stopped.
– Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
– Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0.”
– Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
– Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when ex-
ecuting the WRST instruction immediately after the DWDT instruction.
– Selects the ceramic resonance circuit and stops the on-chip oscillator.
– Selects the RC oscillation circuit and stops the on-chip oscillator.
– Transfers the contents of clock control register MR to register A.
– Transfers the contents of register A to clock control register MR.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
1-101