4501_M Datasheet, PDF (63/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
HARDWARE
LIST OF PRECAUTIONS
15 P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 49➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 49➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 49➂).
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed with
the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 51➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 51➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 51➂).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
Fig. 49 External 0 interrupt program example-1
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
• When the key-on wakeup function of port P13 is not used (regis-
ter K13 = “0”), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 50➀).
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
Fig. 51 External 0 interrupt program example-3
16 _{Power-on reset}
Reset can be automatically performed at power on (power-on reset)
by the built-in power-on reset circuit. When the built-in power-on re-
set circuit is used, the time for the supply voltage to rise from 0 V to
2.0 V must be set to 100 µs or less. If the rising time exceeds 100
µs, connect a capacitor between the RESET pin and VSS at the
shortest distance, and input “L” level to RESET pin until the value of
supply voltage reaches the minimum operating voltage.
LA 0
TI1A
DI
EPOF
POF
; (00✕✕2)
; Input of INT disabled ........................ ➀
; RAM back-up
✕ : these bits are not used here.
Fig. 50 External 0 interrupt program example-2
17 _{Clock control}
Execute the CMCK or the CRCK instruction in the initial setting rou-
tine of program (executing it in addres 0 in page 0 is recommended).
The oscillation circuit by the CMCK or CRCK instruction can be
selected only at once. The oscillation circuit corresponding to the
first executed one of these two instruction is valid. Other oscilla-
tion circuits and the on-chip oscillator stop.
18 _{On-chip oscillator}
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released
from reset is generated by the on-chip oscillator clock. When
considering the oscillation stabilize wait time after system is re-
leased from reset, be careful that the variable frequency of the
on-chip oscillator clock.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
1-51