4501_M Datasheet, PDF (32/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
HARDWARE
FUNCTION BLOCK OPERATIONS
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as fol-
lows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in-
terrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
Interrupt
occurs
Interrupt is
enabled
Interrupt
service routine
•
•
•
•
EI
RTI
• Program counter (PC)
............................................................... Each interrupt address
• Stack register (SK)
..............................................T..h..e...a..d..d..r..e..s.s...o..f...m...a..i.n...r.o..u..t.i.n..e...t.o...b..e.
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
(L→H or
H→L input)
EXF0
V10
Timer 1
underflow
T1F
V12
Timer 2
underflow
T2F
V13
Completion of
A/D conversion
Activated
condition
ADF
Request flag
(state retained)
V 22
Enable
bit
Fig. 15 Interrupt system diagram
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
INTE
Enable
flag
Address C
in page 1
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
1-20