4501_M Datasheet, PDF (135/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
b0 _{Timer 1 interrupt occurrence disabled}
Interrupt control register V1 ✕ 0 ✕ ✕ _{(TV1A instruction)}
➁ Stop Timer Operation
Timer 1 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
b0 _{Timer 1 stop (TW1A instruction)}
Timer control register W1 0 1 0 0 _{Prescaler stop}
Prescaler divided by 16 selected
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown ❈A below.)
Timer 1 reload register R1 “5216” Timer count value 82 set (T1AB instruction)
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F “0”
Timer 1 interrupt activated condition cleared
(SNZT1 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W1 1 1 1 0 ^{Timer 1 operation start (TW1A instruction)}
Prescaler operation start
➅ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
✕1✕✕
Timer 1 interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
Constant period interrupt execution start
❈A The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz)^–1✕ 3
✕ 16 ✕ (82+1)
System clock Instruction Prescaler Timer 1
clock
dividing count
ratio
value
“✕”: it can be “0” or “1.”
Fig. 2.2.3 Timer 1 constant period interrupt setting example
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
2-18