4501_M Datasheet, PDF(139/212 Page) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

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4501_M Datasheet, PDF (139/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

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4501 Group

APPLICATION

2.3 Timers

2.3.2 Related registers

(1) Interrupt control register V1

The external 0 interrupt enable bit is assigned to bit 0, timer 1 interrupt enable bit is assigned to bit

2, and the timer 2 interrupt enable bit is assigned to bit 3.

Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction

can be used to transfer the contents of register V1 to register A.

Table 2.3.1 shows the interrupt control register V1.

Table 2.3.1 Interrupt control register V1

Interrupt control register V1

at reset : 00002

at RAM back-up : 00002

R/W

V13 Timer 2 interrupt enable bit

0 Interrupt disabled (SNZT2 instruction is valid)

1 Interrupt enabled (SNZT2 instruction is invalid) (Note 2)

V12 Timer 1 interrupt enable bit

0 Interrupt disabled (SNZT1 instruction is valid)

1 Interrupt enabled (SNZT1 instruction is invalid) (Note 2)

V11 Not used

This bit has no function, but read/write is enabled.

V10 External 0 interrupt enable bit

0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid) (Note 2)

Notes 1: âRâ represents read enabled, and âWâ represents write enabled.

2: These instructions are equivalent to the NOP instruction.

3: When timer is used, V11 and V10 are not used.

(2) Timer control register W1

The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is

assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler

control bit is assigned to bit 3.

Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction

can be used to transfer the contents of register W1 to register A.

Table 2.3.2 shows the timer control register W1.

Table 2.3.2 Timer control register W1

Timer control register W1

at reset : 00002

at RAM back-up : 00002

W13 Prescaler control bit

0 Stop (state initialized)

1 Operating

Prescaler dividing ratio selection 0 Instruction clock divided by 4

W12

bit

1 Instruction clock divided by 16

W11 Timer 1 control bit

0 Stop (state retained)

1 Operating

Timer 1 count start synchronous 0 Count start synchronous circuit not selected

W10

circuit control bit

1 Count start synchronous circuit selected

Note: âRâ represents read enabled, and âWâ represents write enabled.

R/W

Rev.2.01 Feb 07, 2005

REJ09B0192-0201

2-22

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