4501_M Datasheet, PDF (127/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
APPLICATION
2.1 I/O pins
2.1.4 Notes on use
(1) Note when an I/O port is used as an input port
Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L”
level can be input.
(2) Noise and latch-up prevention
Connect an approximate 0.1 µF bypass capacitor directly to the VSS line and the VDD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM
version.
Connect the CNVSS/VPP pin to VSS through an approximate 5 kΩ resistor which is connected to the
CNVSS/VPP pin at the shortest distance.
(3) Note on multifunction
• The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are
selected.
• The input of P12 can be used even when CNTR (output) is selected.
• The input/output of P20 and P21 can be used even when AIN0, and AIN1 are selected.
(4) Connection of unused pins
Table 2.1.8 shows the connections of unused pins.
(5) SD, RD instructions
When the SD and RD instructions are used, do not set “01002” or more to register Y.
(6) Analog input pins
When both analog input AIN0, AIN1 and I/O port P2 function are used, note the following;
• Selection of analog input pins
Even when P20/AIN0, P21/AIN1 are set to pins for analog input, they continue to function as port P2
input/output. Accordingly, when any of them are used as I/O port and others are used as analog input
pins, make sure to set the outputs of pins that are set for analog input to “1.”
Also, the port input function of the pin functions as an analog input is undefined.
(7) Notes on port P13/INT pin
When the bit 3 of register I1 is cleared, the RAM back-up mode is selected and the input of INT pin
is disabled, be careful about the following notes.
• When the key-on wakeup function of port P13 is not used (register K13 = “0”), clear bits 2 and 3
of register I1 before system enters to the RAM back-up mode.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
2-10