4501_M Datasheet, PDF (134/212 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4501 Group
APPLICATION
2.2 Interrupts
➀ Disable Interrupts
INT interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
b0 _{INT interrupt occurrence disabled}
Interrupt control register V1 ✕ ✕ ✕ ⁰ _{(TV1A instruction)}
➁ Set Port
Port used for INT interrupt is set to input port.
b3
b0
Port P13 output latch 1 ^{✕ ✕ ✕} Set to input (OP1A instruction)
➂ Set Valid Waveform
Valid waveform of INT pin is selected.
Both edges detection selected
b3
b0
Interrupt control register I1 1 ✕ 1 ✕ Both edges detection selected (TI1A instruction)
➃ Execute NOP Instruction
NOP instruction
➄ Clear Interrupt Request
INT interrupt activated condition is cleared.
INT interrupt request flag EXF0 “0”
INT interrupt activated condition cleared
(SNZ0 instruction)
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the
interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
➅ Enable Interrupts
The INT interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
✕
✕✕
b0
1
INT interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE _{“1”}
All interrupts enabled (EI instruction)
“✕”: it can be “0” or “1.”
INT interrupt execution started
Fig. 2.2.2 INT interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
Rev.2.01 Feb 07, 2005
REJ09B0192-0201
2-17