RX64M_15 Datasheet, PDF (76/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (5 / 71)
Address
0008 2204h
0008 2400h
0008 2404h
0008 2408h
0008 240Ch
0008 240Eh
0008 2800h
0008 2804h
0008 2808h
0008 280Ch
0008 2810h
0008 2812h
0008 2813h
0008 2814h
0008 2818h
0008 281Ch
0008 281Dh
0008 281Eh
0008 2820h
0008 2821h
0008 2822h
0008 2840h
0008 2844h
0008 2848h
0008 284Ch
0008 2850h
0008 2852h
0008 2853h
0008 2854h
0008 285Ch
0008 285Dh
0008 285Eh
0008 2860h
0008 2861h
Module
Symbol Register Name
DMAC DMAC74 Interrupt Status Monitor Register
DTC DTC Control Register
DTC DTC Vector Base Register
DTC DTC Address Mode Register
DTC DTC Module Start Register
DTC DTC Status Register
EXDMA EXDMA Source Address Register
C0
EXDMA EXDMA Destination Address Register
C0
EXDMA EXDMA Transfer Count Register
C0
EXDMA EXDMA Block Transfer Count Register
C0
EXDMA EXDMA Transfer Mode Register
C0
EXDMA EXDMA Output Setting Register
C0
EXDMA EXDMA Interrupt Setting Register
C0
EXDMA EXDMA Address Mode Register
C0
EXDMA EXDMA Offset Register
C0
EXDMA EXDMA Transfer Enable Register
C0
EXDMA EXDMA Software Start Register
C0
EXDMA EXDMA Status Register
C0
EXDMA EXDMA External Request Sense Mode Register
C0
EXDMA EXDMA External Request Flag Register
C0
EXDMA EXDMA Peripheral Request Flag Register
C0
EXDMA EXDMA Source Address Register
C1
EXDMA EXDMA Destination Address Register
C1
EXDMA EXDMA Transfer Count Register
C1
EXDMA EXDMA Block Transfer Count Register
C1
EXDMA EXDMA Transfer Mode Register
C1
EXDMA EXDMA Output Setting Register
C1
EXDMA EXDMA Interrupt Setting Register
C1
EXDMA EXDMA Address Mode Register
C1
EXDMA EXDMA Transfer Enable Register
C1
EXDMA EXDMA Software Start Register
C1
EXDMA EXDMA Status Register
C1
EXDMA EXDMA External Request Sense Mode Register
C1
EXDMA EXDMA External Request Flag Register
C1
Register
Symbol
DMIST
DTCCR
DTCVBR
DTCADMOD
DTCST
DTCSTS
EDMSAR
EDMDAR
EDMCRA
EDMCRB
EDMTMD
EDMOMD
EDMINT
EDMAMD
EDMOFR
EDMCNT
EDMREQ
EDMSTS
EDMRMD
EDMERF
EDMPRF
EDMSAR
EDMDAR
EDMCRA
EDMCRB
EDMTMD
EDMOMD
EDMINT
EDMAMD
EDMCNT
EDMREQ
EDMSTS
EDMRMD
EDMERF
Number
of Bits
8
8
32
8
8
16
32
Access
Size
8
8
32
8
8
16
32
Number of Access Cycles
ICLK PCLK ICLK  PCLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
1, 2 BCLK
32
32
1, 2 BCLK
32
32
1, 2 BCLK
16
16
1, 2 BCLK
16
16
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
32
32
1, 2 BCLK
32
32
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
32
32
1, 2 BCLK
32
32
1, 2 BCLK
32
32
1, 2 BCLK
16
16
1, 2 BCLK
16
16
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
32
32
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
8
8
1, 2 BCLK
Related
Function
DMACa
DTCa
DTCa
DTCa
DTCa
DTCa
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
EXDMA
Ca
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 76 of 230