RX64M_15 Datasheet, PDF (74/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (3 / 71)
Address
0008 12CCh
0008 12D0h
0008 12D4h
0008 1300h
0008 1304h
0008 1308h
0008 130Ah
0008 1310h
0008 2000h
0008 2004h
0008 2008h
0008 200Ch
0008 2010h
0008 2013h
0008 2014h
0008 2018h
0008 201Ch
0008 201Dh
0008 201Eh
0008 201Fh
0008 2040h
0008 2044h
0008 2048h
0008 204Ch
0008 2050h
0008 2053h
0008 2054h
0008 205Ch
0008 205Dh
0008 205Eh
0008 205Fh
0008 2080h
0008 2084h
0008 2088h
0008 208Ch
0008 2090h
0008 2093h
0008 2094h
0008 209Ch
0008 209Dh
0008 209Eh
0008 209Fh
0008 20C0h
0008 20C4h
0008 20C8h
0008 20CCh
0008 20D0h
0008 20D3h
Module
Symbol Register Name
ECCRA ECCRAM 1-Bit Error Address Capture Register
M
ECCRA ECCRAM Protection Register 2
M
ECCRA ECCRAM Test Control Register
M
BSC Bus Error Status Clear Register
BSC Bus Error Monitoring Enable Register
BSC Bus Error Status Register 1
BSC Bus Error Status Register 2
BSC Bus Priority Control Register
DMAC0 DMA Source Address Register
DMAC0 DMA Destination Address Register
DMAC0 DMA Transfer Count Register
DMAC0 DMA Block Transfer Count Register
DMAC0 DMA Transfer Mode Register
DMAC0 DMA Interrupt Setting Register
DMAC0 DMA Address Mode Register
DMAC0 DMA Offset Register
DMAC0 DMA Transfer Enable Register
DMAC0 DMA Software Start Register
DMAC0 DMA Status Register
DMAC0 DMA Activation Source Flag Control Register
DMAC1 DMA Source Address Register
DMAC1 DMA Destination Address Register
DMAC1 DMA Transfer Count Register
DMAC1 DMA Block Transfer Count Register
DMAC1 DMA Transfer Mode Register
DMAC1 DMA Interrupt Setting Register
DMAC1 DMA Address Mode Register
DMAC1 DMA Transfer Enable Register
DMAC1 DMA Software Start Register
DMAC1 DMA Status Register
DMAC1 DMA Activation Source Flag Control Register
DMAC2 DMA Source Address Register
DMAC2 DMA Destination Address Register
DMAC2 DMA Transfer Count Register
DMAC2 DMA Block Transfer Count Register
DMAC2 DMA Transfer Mode Register
DMAC2 DMA Interrupt Setting Register
DMAC2 DMA Address Mode Register
DMAC2 DMA Transfer Enable Register
DMAC2 DMA Software Start Register
DMAC2 DMA Status Register
DMAC2 DMA Activation Source Flag Control Register
DMAC3 DMA Source Address Register
DMAC3 DMA Destination Address Register
DMAC3 DMA Transfer Count Register
DMAC3 DMA Block Transfer Count Register
DMAC3 DMA Transfer Mode Register
DMAC3 DMA Interrupt Setting Register
Register
Symbol
Number
of Bits
ECCRAM1ECA
32
D
ECCRAMPRCR
8
2
ECCRAMETST
8
Access
Size
32
8
8
Number of Access Cycles
ICLK PCLK ICLK  PCLK
2 ICLK
2 ICLK
2 ICLK
Related
Function
RAM
RAM
RAM
BERCLR
BEREN
BERSR1
BERSR2
BUSPRI
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
DMAMD
DMOFR
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
8
8
8
8
8
8
16
16
16
16
32
32
32
32
32
32
16
16
16
16
8
8
16
16
32
32
8
8
8
8
8
8
8
8
32
32
32
32
32
32
16
16
16
16
8
8
16
16
8
8
8
8
8
8
8
8
32
32
32
32
32
32
16
16
16
16
8
8
16
16
8
8
8
8
8
8
8
8
32
32
32
32
32
32
16
16
16
16
8
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
Buses
Buses
Buses
Buses
Buses
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
DMACa
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 74 of 230