RX64M_15 Datasheet, PDF (152/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5.3.2
Clock Timing
5. Electrical Characteristics
Table 5.11 BCLK Pin Output, SDCLK Pin Output Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Item
BCLK pin output cycle time
BCLK pin output high pulse width
BCLK pin output low pulse width
BCLK pin output rising time
BCLK pin output falling time
SDCLK pin output cycle time
SDCLK pin output high pulse width
SDCLK pin output low pulse width
SDCLK pin output rising time
SDCLK pin output falling time
Packages with 177 to
144 pins
Packages with 100
pins or less
Packages with 177 to
144 pins
Symbol
t_Bcyc
t_CH
t_CL
t_Cr
t_Cf
t_Bcyc
t_CH
t_CL
t_Cr
t_Cf
Min.
Typ.
Max.
Unit
Test
Conditions
16.6
—
—
ns Figure 5.3
33.2
—
—
ns
3.3
—
3.3
—
—
—
—
—
16.6
—
3.3
—
3.3
—
—
—
—
—
—
ns
—
ns
5
ns
5
ns
—
ns
—
ns
—
ns
5
ns
5
ns
BCLK pin output, SDCLK pin output
t_Bcyc, t_SDcyc
t_CH
t_Cf
t_CL
t_Cr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, C = 30 pF
Figure 5.3 BCLK Pin and SDCLK Pin Output Timing
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 152 of 230