RX64M_15 Datasheet, PDF (69/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
3. Address Space
3.2 External Address Space
The external address space is divided into CS areas (CS0 to CS7) and SDRAM area (SDCS). The CS areas are divided
into up to eight areas (CS0 to CS7), each corresponding to the CSn# signal output from a CSn# (n = 0 to 7) pin.
Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) and SDRAM areas (SDCS)
in on-chip ROM disabled extended mode.
0000 0000h
0008 0000h
000A 4000h
000A 6000h
0010 0000h
RAM
Peripheral I/O registers
Standby RAM
Peripheral I/O registers
Reserved area*¹
0100 0000h
External address space
(CS area)
0800 0000h
1000 0000h
External address space
(SDRAM area)
Reserved area*¹
0100 0000h
01FF FFFFh
0200 0000h
02FF FFFFh
0300 0000h
03FF FFFFh
0400 0000h
04FF FFFFh
0500 0000h
05FF FFFFh
0600 0000h
06FF FFFFh
0700 0000h
07FF FFFFh
0800 0000h
CS7 (16 Mbytes)
CS6 (16 Mbytes)
CS5 (16 Mbytes)
CS4 (16 Mbytes)
CS3 (16 Mbytes)
CS2 (16 Mbytes)
CS1 (16 Mbytes)
SDCS (128 Mbytes)
FF00 0000h
FFFF FFFFh
External address space*²
(CS area)
0FFF FFFFh
FF00 0000h
FFFF FFFFh
CS0 (16 Mbytes)
Note 1. Reserved areas should not be accessed.
Note 2. The CS0 area is disabled in on-chip ROM enabled extended mode.
In this mode, the address space for addresses above 1000 0000h is as shown in figure on this
section, Memory Map in Each Operating Mode.
Figure 3.2
Correspondence between External Address Spaces and CS Areas
(In On-Chip ROM Disabled Extended Mode)
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 69 of 230