 English |
|
|
|
|
|
|
|
| RX64M_15 Datasheet, PDF (182/230 Pages) Renesas Technology Corp – Renesas MCUs | |||
| |||
| ◁ |
RX64M Group
5. Electrical Characteristics
Table 5.30 A/D Converter Trigger Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ⤠VREFH0 ⤠AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Output load conditions: VOH = VCC Ã 0.5, VOL = VCC Ã 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
A/D
A/D converter trigger input pulse width
converter
Note 1. tPBcyc: PCLKB cycle
Symbol
tTRGW
Min.
1.5
Max.
â
Unit*1
tPBcyc
Test
Conditions
Figure 5.43
PCLKB
ADTRG0#,
ADTRG1#
Figure 5.43 A/D Converter Trigger Input Timing
tTRGW
Table 5.31 CAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ⤠VREFH0 ⤠AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Output load conditions: VOH = VCC Ã 0.5, VOL = VCC Ã 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
CAC
Item*1, *2
CACREF input pulse width
tPBcyc ⤠tcac
tPBcyc > tcac
Note 1. tPBcyc: PCLKB cycle
Note 2. tCAC: CAC count clock source cycle
Symbol
tCACREF
Min.*1
4.5tcac +
3tPBcyc
5tcac +
6.5tPBcyc
Max.
â
â
Unit*1
ns
Test
Conditions
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 182 of 230
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese