RX64M_15 Datasheet, PDF (198/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
Table 5.40 ETHERC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.
ETHERC
(RMII)
REF50CK cycle time
REF50CK frequency Typ. 50 MHz
T_ck
20
—
—
REF50CK duty
—
35
REF50CK rise/fall time
T_ckr/ckf
0.5
RMII_xxxx*¹ output delay time
T_co
2.5
RMII_xxxx*² setup time
T_su
3
RMII_xxxx*² hold time
T_hd
1
RMII_xxxx*^1, *² rise/fall time
T_r/T_f
0.5
ET_WOL output delay time
t_WOLd
1
ETHERC
(MII)
ET_TX_CLK cycle time
ET_TX_EN output delay time
t_Tcyc
40
t_TENd
1
ET_ETXD0 to ET_ETXD3 output delay time
t_MTDd
1
ET_CRS setup time
t_CRSs
10
ET_CRS hold time
t_CRSh
10
ET_COL setup time
t_COLs
10
ET_COL hold time
t_COLh
10
ET_RX_CLK cycle time
t_TRcyc
40
ET_RX_DV setup time
t_RDVs
10
ET_RX_DV hold time
t_RDVh
10
ET_ERXD0 to ET_ERXD3 setup time
t_MRDs
10
ET_ERXD0 to ET_ERXD3 hold time
t_MRDh
10
ET_RX_ER setup time
t_RERs
10
ET_RX_ER hold time
t_RESh
10
ET_WOL output delay time
t_WOLd
1
Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0
Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER
Max.
—
50 + 100ppm
65
3.5
15.0
—
—
5
23.5
—
20
20
—
—
—
—
—
—
—
—
—
—
—
23.5
Unit
ns
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
Figure 5.62 to
Figure 5.64
Figure 5.66
—
Figure 5.67
Figure 5.68
—
Figure 5.69
Figure 5.70
Figure 5.71
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 198 of 230