RX64M_15 Datasheet, PDF (117/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (46 / 71)
Address
Module
Symbol Register Name
000C 0050h EDMAC FIFO Depth Register
0
000C 0058h EDMAC Receive Method Control Register
0
000C 0064h EDMAC Transmit FIFO Underflow Counter
0
000C 0068h EDMAC Receive FIFO Overflow Counter
0
000C 006Ch EDMAC Independent Output Signal Setting Register
0
000C 0070h EDMAC Flow Control Start FIFO Threshold Setting Register
0
000C 0078h EDMAC Receive Data Padding Insert Register
0
000C 007Ch EDMAC Transmit Interrupt Setting Register
0
000C 00C8h EDMAC Receive Buffer Write Address Register
0
000C 00CCh EDMAC Receive Descriptor Fetch Address Register
0
000C 00D4h EDMAC Transmit Buffer Read Address Register
0
000C 00D8h EDMAC Transmit Descriptor Fetch Address Register
0
000C 0100h ETHER ETHERC Mode Register
C0
000C 0108h ETHER Receive Frame Length Register
C0
000C 0110h ETHER ETHERC Status Register
C0
000C 0118h ETHER ETHERC Interrupt Enable Register
C0
000C 0120h ETHER PHY Interface Register
C0
000C 0128h ETHER PHY Status Register
C0
000C 0140h ETHER Random Number Generation Counter Upper Limit
C0
Setting Register
000C 0150h ETHER IPG Register
C0
000C 0154h ETHER Automatic PAUSE Frame Register
C0
000C 0158h ETHER Manual PAUSE Frame Register
C0
000C 0160h ETHER Received PAUSE Frame Counter
C0
000C 0164h ETHER PAUSE Frame Retransmit Count Setting Register
C0
000C 0168h ETHER PAUSE Frame Retransmit Counter
C0
000C 016Ch ETHER Broadcast Frame Receive Count Setting Register
C0
000C 01C0h ETHER MAC Address Upper Bit Register
C0
000C 01C8h ETHER MAC Address Lower Bit Register
C0
000C 01D0h ETHER Transmit Retry Over Counter Register
C0
000C 01D4h ETHER Late Collision Detect Counter Register
C0
000C 01D8h ETHER Lost Carrier Counter Register
C0
Register
Symbol
FDR
RMCR
TFUCR
RFOCR
IOSR
FCFTR
RPADIR
TRIMD
RBWAR
RDFAR
TBRAR
TDFAR
ECMR
RFLR
ECSR
ECSIPR
PIR
PSR
RDMLR
IPGR
APR
MPR
RFCF
TPAUSER
TPAUSECR
BCFRR
MAHR
MALR
TROCR
CDCR
LCCR
Number
of Bits
32
Access
Size
32
Number of Access Cycles
ICLK PCLK ICLK  PCLK
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
4, 5 PCLKA
2, 3 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
32
32
13, 14 PCLKA
2 to 7 ICLK
Related
Function
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
EDMAC
a
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
ETHER
C
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 117 of 230