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RX64M_15 Datasheet, PDF (149/230 Pages) Renesas Technology Corp – Renesas MCUs
RX64M Group
5.3 AC Characteristics
5. Electrical Characteristics
Table 5.7 Operating Frequency (High-Speed Operating Mode)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Operating
frequency
System clock (ICLK)
Peripheral module clock (PCLKA)
f
—
—
—
—
Peripheral module clock (PCLKB)
—
—
Peripheral module clock (PCLKC)
—
—
Peripheral module clock (PCLKD)
—
—
Flash-IF clock (FCLK)
—*1
—
External bus clock (BCLK) Packages with 177 to 144 pins
only
—
—
Package with 100 pins only
—
—
BCLK pin output
Packages with 177 to 144 pins
only
—
—
Package with 100 pins only
—
—
SDRAM clock (SDCLK)
Packages with 177 to 144 pins
only
—
—
SDCLK pin output
Packages with 177 to 144 pins
only
—
—
Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents.
Max.
120
120
60
60
60
60
120
60
60
30
60
60
Unit
MHz
Table 5.8 Operating Frequency (Low-Speed Operating Mode 1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Operating
frequency
System clock (ICLK)
Peripheral module clock (PCLKA)
f
—
—
1
MHz
—
—
1
Peripheral module clock (PCLKB)
—
—
1
Peripheral module clock (PCLKC)*1
—
—
1
Peripheral module clock (PCLKD)*1
—
—
1
Flash-IF clock (FCLK)
—
—
1
External bus clock (BCLK) Packages with 177 to 144 pins
only
—
—
1
Package with 100 pins only
—
—
1
BCLK pin output
Packages with 177 to 144 pins
only
—
—
1
Package with 100 pins only
—
—
1
SDRAM clock (SDCLK)
Packages with 177 to 144 pins
only
—
—
1
SDCLK pin output
Packages with 177 to 144 pins
only
—
—
1
Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz.
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 149 of 230