RX64M_15 Datasheet, PDF (197/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
Table 5.39 MMC Host Interface Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.*¹
Max.
Unit
Test
Conditions*²
MMCIF MMC_CLK clock cycle
MMC_CLK clock high level width
MMC_CLK clock low level width
MMC_CLK clock rising time
MMC_CLK clock falling time
MMC_CMD, MMC_D7 to MMC_D0 output data delay
(data transfer mode)
t_MMCPP
t_MMCWH
t_MMCWL
t_MMCLH
t_MMCHL
t_MMCODLY
2 × t_PBcyc
6.5
6.5
—
—
–6.5
—
ns Figure 5.61
—
ns
—
ns
5
ns
5
ns
6.5
ns
MMC_CMD, MMC_D7 to MMC_D0 input data setup
t_MMCISU
8
MMC_CMD, MMC_D7 to MMC_D0 input data hold
t_MMCIH
2
—
ns
—
ns
Note 1. t_PBcyc: PCLKB cycle
Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.
For the MMC interface, the AC portion of the electrical characteristics is measured for each group.
tMMCPP
tMMCWL
tMMCWH
MMC_CLK
tMMCHL
MMC_CMD,
MMC_D7 to MMC_D0 input
tMMCLH
tMMCISU tMMCIH
MMC_CMD,
MMC_D7 to MMC_D0 output
Figure 5.61 MMC Interface
tMMCODLY (max)
tMMCODLY (min)
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 197 of 230