RX64M_15 Datasheet, PDF (157/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.18 Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Item
Recovery time
after
cancellation of
software
standby
mode*¹
Crystal
resonator
connected to
main clock
oscillator
Main clock
oscillator
operating
Main clock
oscillator and
PLL circuit
operating
Symbol Min. Typ.
t_SBYMC — —
Max.
t_SBYOSCWT*²
t_SBYSEQ*³
Unit
Test
Conditions
{( MSTS[7:0] bits × 100 μs + 7/f_ICLK + μs Figure 5.12
32 ) + 76 } / 0.216
2n/f_MAIN
t_SBYPC
{( MSTS[7:0] bits × 100 μs + 7/f_ICLK +
32 ) + 138 } / 0.216
2n/f_PLL
External clock Main clock
input to main oscillator
clock oscillator operating
t_SBYEX
352
100 μs + 7/f_ICLK +
2n/f_EXMAIN
Main clock
oscillator and
PLL circuit
operating
t_SBYPE
639
100 μs + 7/f_ICLK +
2n/f_PLL
Sub-clock oscillator operating t_SBYSC
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating
t_SBYHO
{( SSTS[7:0] bits ×
16384 ) + 13 } /
0.216 + 10/f_FCLK
454
100 μs + 4/f_ICLK +
2n/f_SUB
100 μs + 7/f_ICLK +
2n/f_HOCO
High-speed
on-chip
oscillator
operating and
PLL circuit
operating
t_SBYPH
741
100 μs + 7/f_ICLK +
2n/f_PLL
Low-speed on-chip oscillator
operating*⁴
t_SBYLO
338
100 μs + 7/f_ICLK +
2n/f_LOCO
Note 1.
Note 2.
Note 3.
Note 4.
The time for return after release from software standby is determined by the value obtained by adding the oscillation stabilization
waiting time (t_SBYOSCWTO) and the time required for operations by the software standby release sequencer (t_SBYSEQ).
When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time t_SBYOSCWT is selected.
For n, the greatest value is selected from among the internal clock division settings.
This condition applies when f_ICLK:f_FCLK = 1:1, 2:1, or 4:1.
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 157 of 230