RX64M_15 Datasheet, PDF (3/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
1. Overview
Table 1.1
Outline of Specifications (2/9)
Classification
Clock
Module/Function
Clock generation circuit
Reset
Power-on reset
Voltage detection circuit (LVDA)
Low power
consumption
Low power consumption
facilities
Battery backup function
Description
 Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
 The peripheral module clocks can be set to frequencies above that of the system clock.
 Main-clock oscillation stoppage detection
 Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and
external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK): Up
to 120 MHz
Peripheral modules of MTU3, GPT, RSPI, SCIFA, USBA, ETHERC, EPTPC, EDMAC,
and AES run in synchronization with PCLKA, which operates at up to 120 MHz.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
ADCLK in the SD12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz
ADCLK in the SD12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 60 MHz
 Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a
reference clock of the PLL circuit
Nine types of reset
 RES# pin reset: Generated when the RES# pin is driven low.
 Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =
AVCC1 rises.
 Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.
 Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.
 Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.
 Deep software standby reset: Generated in response to an interrupt to trigger release
from deep software standby.
 Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
 Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh
error occurs.
 Software reset: Generated by register setting.
If the RES# pin is at the high level when power is supplied, an internal reset is generated.
After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified
period has elapsed, the reset is cancelled.
Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an
internal reset or internal interrupt.
 Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, and 2.80
V)
 Voltage detection circuits 1 and 2
Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, and 2.85
V)
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
 Two types of timing are selectable for release from reset
An internal interrupt can be requested.
 Detection of voltage rising above and falling below thresholds is selectable.
 Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
 Module stop function
 Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
 When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied
to keep the real-time clock (RTC) operating.
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
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