RX64M_15 Datasheet, PDF (192/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
Table 5.36 RIIC Timing (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.*^1, *²
Max.
Unit
Test
Conditions
RIIC
SCL input cycle time
(Standard-mode,
SMBus)
SCL input high pulse width
ICFER.FMPE = 0 SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
RIIC
SCL input cycle time
(Fast-mode)
ICFER.FMPE = 0
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
t_SCL
t_SCLH
t_SCLL
t_Sr
6(12) × t_IICcyc + 1300
3(6) × t_IICcyc + 300
3(6) × t_IICcyc + 300
—
—
0
3(6) × t_IICcyc + 300
t_IICcyc + 300
1000
1000
t_IICcyc + 50
0
—
6(12) × t_IICcyc + 600
3(6) × t_IICcyc + 300
3(6) × t_IICcyc + 300
20 × (External pull-up
voltage/5.5V)
—
—
—
1000
300
1(4) × t_IICcyc
—
—
—
—
—
—
400
—
—
—
300
ns Figure 5.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
ns
SCL, SDA input fall time
t_Sf
20 × (External pull-up
300
ns
voltage/5.5V)
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
t_SP
t_BUF
t_STAH
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
0
3(6) × t_IICcyc + 300
t_IICcyc + 300
300
300
t_IICcyc + 50
0
—
1(4) × t_IICcyc ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
400
pF
Note: t_IICcyc: RIIC internal reference clock (IIC) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 192 of 230