RX64M_15 Datasheet, PDF (156/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
Table 5.16 PLL Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Item
PLL clock oscillation frequency
PLL clock oscillation stabilization wait time
Symbol
f_PLL
t_PLLWT
Min.
Typ.
Max.
Unit
Test
Conditions
120
—
240
MHz
—
259
320
μs Figure 5.10
PLLCR2.PLLEN
PLL circuit output
OSCOVFSR.PLOVF
PLL clock
t_PLLWT
Figure 5.10 PLL Clock Oscillation Start Timing
Table 5.17 Sub-Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
V_BATT = 2.0 to 3.6 V, T_a = T_opr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Sub-clock oscillation frequency
Sub-clock oscillation stabilization time
Sub-clock oscillation stabilization wait time
f_SUB
—
32.768
—
t_SUBOSC
—
—
*¹
t_SUBOSCWT
—
—
*²
kHz
s Figure 5.11
s
Note 1.
Note 2.
When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization
wait time in accord with the formula below.
t_SUBOSCWT = [(SSTS[7:0] bits × 16384) + 10] / f_LOCO
SOSCCR.SOSTP
Sub-clock oscillator output
OSCOVFSR.SOOVF
t_SUBOSC
t_SUBOSCWT
Sub-clock
Figure 5.11 Sub-Clock Oscillation Start Timing
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
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