RX64M_15 Datasheet, PDF (178/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
Table 5.25 TMR Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.
TMR
Timer clock pulse width
Single-edge
t_TMCWH,
1.5
setting
t_TMCWL
Both-edge
2.5
setting
Note 1. t_PBcyc: PCLKB cycle
Max.
—
—
Unit*¹
t_PBcyc
Test
Conditions
Figure 5.36
PCLKB
TMCI0 to TMCI3
t_TMCWL
Figure 5.36 TMR Clock Input Timing
t_TMCWH
Table 5.26 CMTW Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, T_a = T_opr
Output load conditions: V_OH = VCC × 0.5, V_OL = VCC × 0.5, C = 30 pF
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.
CMTW
Input capture input pulse
Single-edge
t_CMTWTICW
1.5
width
setting
Both-edge
2.5
setting
Note 1. t_PBcyc: PCLKB cycle
Max.
—
—
Unit*¹
t_PBcyc
Test
Conditions
Figure 5.37
PCLKB
Input capture
input
Figure 5.37 CMTW Input Capture Input Timing
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
t_CMTWICW
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