RX64M_15 Datasheet, PDF (211/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
5. Electrical Characteristics
5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.50 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = V_BATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,
T_a = T_opr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Voltage detection Power-on
Low power consumption
V_POR
2.5
2.6
2.7
V Figure 5.79
level
reset (POR) function disabled*¹
Low power consumption
function enabled*²
2.0
2.35
2.7
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Internal reset time Power-on reset time
LVD0 reset time
LVD1 reset time
LVD2 reset time
Minimum VCC down time
V_{det0_1}
V_{det0_2}
V_{det0_3}
V_{det1_1}
V_{det1_2}
V_{det1_3}
V_{det2_1}
V_{det2_2}
V_{det2_3}
t_POR
t_LVD0
t_LVD1
t_LVD2
t_VOFF
2.84
2.77
2.70
2.89
2.82
2.75
2.89
2.82
2.75
—
—
—
—
200
2.94
2.87
2.80
2.99
2.92
2.85
2.99
2.92
2.85
4.6
0.70
0.57
0.57
—
3.04
2.97
2.90
3.09
3.02
2.95
3.09
3.02
2.95
—
—
—
—
—
Figure 5.80
Figure 5.81
Figure 5.82
ms Figure 5.79
Figure 5.80
Figure 5.81
Figure 5.82
μs Figure 5.79,
Figure 5.80
Response delay time
t_det
—
—
200
μs Figure 5.79 to
Figure 5.82
LVD operation stabilization time (after LVD is enabled)*³
Hysteresis width (LVD1 and LVD2)
T_d(E-A)
—
—
10
μs Figure 5.81,
V _LVH
—
80
—
mV ^{Figure 5.82}
Note:
Note 1.
Note 2.
Note 3.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det1,
and V_det2 for the POR/ LVD.
The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.
The low power consumption function is enabled and DEEPCUT[1:0] = 11b.
The voltage of VCC = AVCC0 = AVCC1 when LVD1 is enabled must be set to at least 80 mV above the maximum value of the
voltage detection 1 level (V_{det1_1, 2, 3}) selected by the LVDLVLR.LVD1LVL[3:0] bits.
Similarly, the voltage of VCC = AVCC0 = AVCC1 when LVD2 is enabled must be set to at least 80 mV above the maximum
value of the voltage detection 2 level (V_{det2_1, 2, 3}) selected by the LVDLVLR.LVD2LVL[3:0] bits.
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 211 of 230