RX64M_15 Datasheet, PDF (5/230 Pages) Renesas Technology Corp – Renesas MCUs

RX64M Group
1. Overview
Table 1.1
Outline of Specifications (4/9)
Classification
Timers
Timers
Module/Function
16-bit timer pulse unit
(TPUa)
Multifunction timer pulse
unit (MTU3a)
Port output enable 3
(POE3a)
Description
 (16 bits × 6 channels) × 1 unit
 Maximum of 16 pulse-input/output possible
 Select from among seven or eight counter-input clock signals for each channel
 Input capture/output compare function
 Output of PWM waveforms in up to 15 phases in PWM mode
 Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
 PPG output trigger can be generated
 Capable of generating conversion start triggers for the A/D converters
 Digital filtering of signals from the input capture pins
 Event linking by the ELC
 9 channels (16 bits × 8 channels, 32 bits × 1 channel)
 Maximum of 16 pulse-input/output and 3 pulse-input possible
 Select from among 13 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD)
11 of the signals are available for channels 1, 3 and 4, 12 are available for channel 2,
and 9 are available for channels 5 to 8.
 Input capture function
 39 output compare/input capture registers
 Counter clear operation (synchronous clearing by compare match/input capture)
 Simultaneous writing to multiple timer counters (TCNT)
 Simultaneous register input/output by synchronous counter operation
 Buffered operation
 Support for cascade-connected operation
 43 interrupt sources
 Automatic transfer of register data
 Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
 Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
 Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
 Counter functionality for dead-time compensation
 Generation of triggers for A/D converter conversion
 A/D converter start triggers can be skipped
 Digital filter function for signals on the input capture and external counter clock pins
 PPG output trigger can be generated
 Event linking by the ELC
 Control of the high-impedance state of the MTU3/GPT's waveform output pins
 5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11
 Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
 Initiation by oscillation-stoppage detection or software
 Additional programming of output control target pins is enabled
R01DS0173EJ0100 Rev.1.00
Jul 31, 2014
Page 5 of 230