4583 Datasheet, PDF (69/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
17 _{A/D converter-1}
• When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
• Clear the bit 2 of register V2 to “0” to change the operating mode of
the A/D converter from the comparator mode to A/D conversion mode.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the com-
parator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
LA 8
TV2A
LA 0
TQ1A
SNZAD
NOP
; (✕0✕✕2)
; The SNZAD instruction is valid ........ ➀
; (0✕✕✕2)
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
✕ : these bits are not used here.
Fig. 65 A/D converter program example-3
18 _{A/D converter-2}
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog volt-
age is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may
not be obtained. Therefore, reduce the impedance or, connect a
capacitor (0.01 µF to 1 µF) to analog input pins (Figure 66).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 67. In addition, test
the application products sufficiently.
Sensor
AI N
19 _{POF instruction}
When the POF instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when ex-
ecuting only the POF instruction.
Be sure to disable interrupts by executing the DI instruction be-
fore executing the EPOF instruction and the POF instruction
continuously.
20 _{Program counter}
Make sure that the PC does not specify after the last page of the
built-in ROM.
21 _{Power-on reset}
When the built-in power-on reset circuit is used, the time for the
supply voltage to rise from 0 V to the value of supply voltage or
more must be set to 100 µs or less. If the rising time exceeds 100
µs, connect a capacitor between the RESET pin and VSS at the
shortest distance, and input “L” level to RESET pin until the value
of supply voltage reaches the minimum operating voltage.
22 _{Note on voltage drop detection circuit}
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 68);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
VDD
Recommended
operatng condition
min.value
VVRRSSTT^+–
No reset
Program failure may occur.
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 66 Analog input external circuit example-1
VDD
Recommended
operatng condition
min.value
VVRRSSTT^+–
Fig. 68 VDD and VRST^–
Reset
→ Normal operation
Sensor
About 1kΩ
AI N
Fig. 67 Analog input external circuit example-2
Rev.3.00 Aug 06, 2004 page 69 of 151
REJ03B0009-0300Z