4583 Datasheet, PDF (53/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(2) Internal state at reset
Figure 43 and 44 show internal state at reset (they are the same af-
ter system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure are undefined, so set the
initial value to them.
• Program counter (PC) ..............................................................................0......0......0.......0......0... 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• External 1 interrupt request flag (EXF1) .............................................................................. 0
• Interrupt control register V1 ..................................................................................0.......0......0... 0
• Interrupt control register V2 ..................................................................................0.......0......0... 0
• Interrupt control register I1 ...................................................................................0.......0......0... 0
• Interrupt control register I2 ...................................................................................0.......0......0... 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Timer 3 interrupt request flag (T3F) ..................................................................................... 0
• Timer 4 interrupt request flag (T4F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
• Timer control register W1 .....................................................................................0.......0......0... 0
• Timer control register W2 .....................................................................................0.......0......0... 0
• Timer control register W3 .....................................................................................0.......0......0... 0
• Timer control register W4 .....................................................................................0.......0......0... 0
• Timer control register W5 .....................................................................................0.......0......0... 0
• Timer control register W6 .....................................................................................0.......0......0... 0
• Clock control register MR .....................................................................................1.......1......1... 1
• Clock control register RG ..................................................................................................... 0
• 8-bit general register SI ...............................................................✕......✕.......✕......✕......✕.......✕......✕... ✕
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................0.......0......0... 0
• A/D control register Q2 .........................................................................................0.......0......0... 0
• A/D control register Q3 .........................................................................................0.......0......0... 0
• Successive comparison register AD .............................✕........✕......✕......✕.......✕......✕......✕.......✕......✕... ✕
• Comparator register .....................................................................✕......✕.......✕......✕......✕.......✕......✕... ✕
• Key-on wakeup control register K0 ......................................................................0.......0......0... 0
• Key-on wakeup control register K1 ......................................................................0.......0......0... 0
• Key-on wakeup control register K2 ......................................................................0.......0......0... 0
• Pull-up control register PU0 .................................................................................0.......0......0... 0
• Pull-up control register PU1 .................................................................................0.......0......0... 0
00000000
(Interrupt disabled)
(Interrupt disabled)
(Interrupt disabled)
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
(Timer 3 stopped)
(Timer 4 stopped)
(Period measurement circuit stopped)
(On-chip oscillator operating)
“✕” represents undefined.
Fig. 43 Internal state at reset 1
Rev.3.00 Aug 06, 2004 page 53 of 151
REJ03B0009-0300Z