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4583 Datasheet, PDF (28/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
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4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(5) Notes on External 1 interrupt
â Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in software, be careful about the following notes.
â Note on bit 2 of register I2
When the interrupt valid waveform of the P31/INT1 pin is
changed with the bit 2 of register I2 in software, be careful about
the following notes.
⢠Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 3 of regis-
ter I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to â0â (refer to
Figure 21â) and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to â0â after executing at least one instruction (refer to Figure
21â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 21â).
⢠Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the bit 2 of regis-
ter I2 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 1 of register V1 to â0â (refer to
Figure 23â) and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to â0â after executing at least one instruction (refer to Figure
23â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 23â).
LA 4
TV1A
LA 8
TI2A
NOP
SNZ1
NOP
; (ââ0â2)
; The SNZ1 instruction is valid ........... â
; (1âââ2)
; Control of INT1 pin input is changed
........................................................... â
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... â
LA 4
TV1A
LA 12
TI2A
NOP
SNZ1
NOP
; (ââ0â2)
; The SNZ1 instruction is valid ........... â
; (â1ââ2)
; Interrupt valid waveform is changed
........................................................... â
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 21 External 1 interrupt program example-1
â : these bits are not used here.
Fig. 23 External 1 interrupt program example-3
â Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared to â0â , the RAM back-up
mode is selected and the input of INT1 pin is disabled, be careful
about the following notes.
⢠When the input of INT1 pin is disabled (register I23 = â0â), set the
key-on wakeup function to be invalid (register K22 = â0â) before
system enters to the RAM back-up mode. (refer to Figure 22â).
LA 0
TK2A
DI
EPOF
POF
; (â0ââ2)
; Input of INT1 key-on wakeup invalid .. â
; RAM back-up
â : these bits are not used here.
Fig. 22 External 1 interrupt program example-2
Rev.3.00 Aug 06, 2004 page 28 of 151
REJ03B0009-0300Z
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