4583 Datasheet, PDF (59/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 18 Key-on wakeup control register, pull-up control register
Key-on wakeup control register K0
at reset : 00002
at RAM back-up : state retained
Pins P12 and P13 key-on wakeup
K03
control bit
Pins P10 and P11 key-on wakeup
K02
control bit
Pins P02 and P03 key-on wakeup
K01
control bit
Pins P00 and P01 key-on wakeup
K00
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
Key-on wakeup control register K1
at reset : 00002
at RAM back-up : state retained
Ports P02 and P03 return condition selection 0
K13
bit
1
Ports P02 and P03 valid waveform/
0
K12
level selection bit
1
Ports P01 and P00 return condition selection 0
K11
bit
1
Ports P01 and P00 valid waveform/
0
K10
level selection bit
1
Return by level
Return by edge
Falling waveform/“L” level
Rising waveform/“H” level
Return by level
Return by edge
Falling waveform/“L” level
Rising waveform/“H” level
Key-on wakeup control register K2
at reset : 00002
at RAM back-up : state retained
0
K23 INT1 pin return condition selection bit
1
0
K22 INT1 pin key-on wakeup contro bit
1
0
K21 INT0 pin return condition selection bit
1
0
K20 INT0 pin key-on wakeup contro bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
Return by level
Return by edge
Key-on wakeup not used
Key-on wakeup used
Return by level
Return by edge
Key-on wakeup not used
Key-on wakeup used
R/W
TAK0/TK0A
R/W
TAK1/TK1A
R/W
TAK2/TK2A
Rev.3.00 Aug 06, 2004 page 59 of 151
REJ03B0009-0300Z