4583 Datasheet, PDF (52/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(1) Power-on reset
Reset can be automatically performed at power on (power-on re-
set) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V until the value of supply voltage reaches the minimum
operating voltage must be set to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and VSS at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
100 ∝s or less
VDD (Note 3)
(Note 1)
(Note 2)
RESET pin
(Note 1)
Pull-up transistor
Internal reset signal
Power-on reset circuit
Voltage drop detection circuit
Watchdog reset signal
Power-on reset circuit output
Internal reset signal
WEF
SRST instruction
Reset
state
Power-on Reset released
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 42 Structure of reset pin and its peripherals, and power-on reset operation
Table 14 Port state at reset
Name
D0–D5
D6/CNTR0
C/CNTR1
P00–P03
P10–P13
P20, P21, P22
P30/INT0, P31/INT1
P60/AIN0, P61/AIN1, P62, P63
Function
D0–D5
D6
C
P00–P03
P10–P13
P20–P22
P30, P31
P60–P63
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
“L” (VSS) level
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Note 1)
High-impedance (Note 1)
High-impedance (Note 1)
Rev.3.00 Aug 06, 2004 page 52 of 151
REJ03B0009-0300Z