4583 Datasheet, PDF (5/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MULTIFUNCTION
Pin
D6
C
P30
P31
Multifunction
CNTR0
CNTR1
INT0
INT1
Pin
CNTR0
CNTR1
INT0
INT1
Multifunction
D6
C
P30
P31
Pin
P60
P61
Multifunction
AIN0
AIN1
Notes 1: Pins except above have just single function.
2: The input/output of P30 and P31 can be used even when INT0 and INT1 are selected.
3: The input/output of D6 can be used even when CNTR0 (input) is selected.
4: The input of D6 can be used even when CNTR0 (output) is selected.
5: The “H” output of C can be used even when CNTR1 (output) is selected.
Pin
AIN0
AIN1
Multifunction
P60
P61
DEFINITION OF CLOCK AND CYCLE
q Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XIN)) by the external quartz-crystal oscillation
Table Selection of system clock
Register MR
System clock
MR3 MR2 MR1 MR0
0
0
0
0 f(STCK) = f(XIN)
✕
1 f(STCK) = f(RING)
0
1
0
0 f(STCK) = f(XIN)/2
✕
1 f(STCK) = f(RING)/2
1
0
0
0 f(STCK) = f(XIN)/4
✕
1 f(STCK) = f(RING)/4
1
1
0
0 f(STCK) = f(XIN)/8
✕
1 f(STCK) = f(RING)/8
✕: 0 or 1
Note: The f(RING)/8 is selected after system is released from reset.
When on-chip oscillator clock is selected for main clock, set
the on-chip oscillator to be operating state.
q System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
q Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle gen-
erates the one machine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
XIN through mode
Ring through mode
XIN divided by 2 mode
Ring divided by 2 mode
XIN divided by 4 mode
Ring divided by 4 mode
XIN divided by 8 mode
Ring divided by 8 mode
Rev.3.00 Aug 06, 2004 page 5 of 151
REJ03B0009-0300Z