4583 Datasheet, PDF (17/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table refer-
ence instruction (TABP p) is executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which speci-
fies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, reg-
ister X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
Program counter
p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
Register Y (4) Specifying
RAM digit
Register X (4) Specifying RAM file
Register Z (2)
Specifying RAM file group
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
00 01
Register Y (4)
D3 D2 D1 D0
1
Port D output latch
Fig. 9 SD instruction execution example
Rev.3.00 Aug 06, 2004 page 17 of 151
REJ03B0009-0300Z