4583 Datasheet, PDF (55/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
(1) SVDE instruction
When the SVDE instruction is executed, the voltage drop detec-
tion circuit is valid even after system enters into the RAM
back-up mode. The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the
system reset is required.
S
QR
EPOF instruction +
POF instruction
Internal reset signal
Key-on wakeup signal
•
–
VRST ⁺
VRST ^-
+
Voltage drop detection circuit
Fig. 45 Voltage drop detection reset circuit
VDD
VRST+(reset release voltage)
VRST ^-(reset voltage)
QS
R
SVDE instruction
Internal reset signal
VDCE
Voltage drop detection circuit
Reset signal
Voltage drop detection circuit
Reset signal
RESET pin
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 120 to 144 times.
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).
Fig. 46 Voltage drop detection circuit operation waveform
Table 15 Voltage drop detection circuit operation state
VDCE pin
At CPU operating
At RAM back-up
(SVDE instruction not executed)
“L”
Invalid
Invalid
“H”
Valid
Invalid
At RAM back-up
(SVDE instruction executed)
Invalid
Valid
(2) Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 47);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
Rev.3.00 Aug 06, 2004 page 55 of 151
REJ03B0009-0300Z
VDD
Recommended
operatng condition
min.value
VVRRSSTT⁺_–
VDD
Recommended
operatng condition
min.value
VVRRSSTT⁺_–
Fig. 47 VDD and VRST–
No reset
Program failure may occur.
→ Normal operation
Reset