4583 Datasheet, PDF (32/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
C/CNTR1
P31/INT1
I23
I20
W33
T3UDF
PWMOUT
ORCLK
T2UDF
W63
0
1
W31, W30
00
01
10
11
W32
I22
One-sided edge ^I21
0
detection circuit
0
1
Both edges
1
detection circuit
(Note 4)
SQ
R
Timer 3 (8)
(TAB3)
Reload register R3 (8)
(T3AB) (TR3AB) (T3AB)
(T3AB)
Register B Register A
(TAB3)
PWMOUT
Port C output
I20
1
0
Timer 3
T3F
interrupt
Timer 3
underflow signal
(T3UDF)
W30 W31
QD
W32 ^{R T}
T3UDF
W61
XIN
ORCLK
(Note 3)
W40
0
1/2
1
W41
(TAB4)
Register B Register A
(T4HAB)
Reload register R4H (8)
Reload control circuit
Timer 4 (8)
“H” interval expansion
(T4R4L)
Reload register R4L (8)
(T4AB)
(T4AB)
(T4AB)
Register B Register A
(TAB4)
TQ
PWMOD
W42
R _W43
1
T4F Timer 4
0
interrupt
INSTCK
Watchdog timer
1 - - - - - - - - - - - - - - 16
(Note 5)
SQ
WDF1
WRST instruction _R
RESET signal S Q
(Note 7)
WEF
DWDT instruction R
+
WRST instruction
(Note 6)
D Q Watchdog reset signal
T R ^{RESET signal}
TR3AB: This instruction is used to transfer the contents of
register A and register B to only reload register R3.
T4R4L: This instruction is used to transfer the contents of
Notes 3: XIN cannot be used for the count source when bit 1 (MR1) of
register MR is set to “1” and f(XIN) oscillation is stopped.
reload register R4L to timer 4.
4: Timer 3 count start synchronous circuit is set by the valid edge
INSTCK: Instruction clock (system clock divided by 3)
ORCLK: Prescaler output (instruction clock divided by 1 to 256)
of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2.
5: Flag WDF1 is cleared to “0” and the next instruction is skipped
Data is set automatically from each reload
register when timer underflows
when the WRST instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST
(auto-reload function).
instruction is executed while flag WDF1 = “0”.
6: Flag WEF is cleared to “0” and watchdog timer reset does not
occur when the DWDT instruction and WRST instruction are
executed continuously.
7: The WEF flag is set to “1” at system reset or RAM back-up
mode.
Fig. 26 Timer structure (2)
Rev.3.00 Aug 06, 2004 page 32 of 151
REJ03B0009-0300Z