4583 Datasheet, PDF (104/153 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
D9
D0
Number of
1001111001
279
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
Grouping:
Description:
A/D conversion operation
In the A/D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9–AD6) of
register AD to register B, and the middle-or-
der 4 bits (AD5–AD2) of register AD to
register A. In the comparator mode (Q13 = 1),
transfers the middle-order 4 bits (AD7–AD4)
of register AD to register B, and the low-order
4 bits (AD3–AD0) of register AD to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
D9
D0
Number of Number of Flag CY
words
cycles
0 0 0 0 1 0 1 0 1 0 ₂ 0 2 A ₁₆
1
1
–
Skip condition
–
Operation:
(B) ← (E7–E4)
(A) ← (E3–E0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
D9
D0
Number of Number of Flag CY
0
0
1
0
p5 p4 p3 p2 p1 p0
2
0
8
+p
p
16
words
1
cycles
3
–
Skip condition
–
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(DR2) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
Note: p is 0 to 127 for Grouping: Arithmetic operation
M34583MD/ED.
Description: Transfers bits 9 and 8 to register D, bits 7 to 4
When this instruction
to register B and bits 3 to 0 to register A.
is executed, be careful
These bits 7 to 0 are the ROM pattern in ad-
not to over the stack
dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
because 1 stage of
by registers A and D in page p.
stack register is used.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
(PC) ← (SK(SP))
(SP) ← (SP) – 1
after system is released from reset or re-
turned from RAM back-up: 0 to 63.
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction
code
D9
D0
Number of Number of Flag CY
1001110101
275
words
cycles
2
16
1
1
–
Skip condition
–
Operation:
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (TPS7–
TPS4) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
Rev.3.00 Aug 06, 2004 page 104 of 151
REJ03B0009-0300Z