M306H2MC-XXXFP Datasheet, PDF (54/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits
at a time. Figure 2.7.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack
pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even) Program counter (PCL)
[SP] – 3 (Odd) ^{Program counter (PCM)}
(2) Saved simultaneously,
all 16 bits
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
Flag register Program
(FLGH) counter (PCH)
(1) Saved simultaneously,
all 16 bits
[SP] (Even)
Finished saving registers
in two operations.
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
[SP] – 2(Odd)
Program counter (PCM)
Flag register (FLGL)
(4) _{Saved simultaneously,}
all 8 bits
(1)
[SP] – 1 (Even)
Flag register
(FLGH)
Program
counter (PCH)
(2)
[SP] (Odd)
Finished saving registers
in four operations.
Figure 2.7.7 Operation of saving registers
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt
request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Rev. 1.0
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