M306H2MC-XXXFP Datasheet, PDF (51/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
2.7.6 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to
the instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruc-
tion, the processor temporarily suspends the instruction being executed, and transfers control to the
interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 0000016.
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (Dflag), and the stack pointer select flag
(U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt
numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
( f) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the
first address of the interrupt routine.
Note: This register cannot be utilized by the user.
(1) Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and
the time required for executing the interrupt sequence (b). Figure 2.7.4 shows the interrupt response
time.
Interrupt request generated Interrupt request acknowledged
Instruction
(a)
Interrupt sequence
(b)
Time
Instruction in
interrupt routine
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 2.7.4 Interrupt response time
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