M306H2MC-XXXFP Datasheet, PDF (30/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protectregister (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting
the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK
cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcom-
puter has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two
or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set
this bit after referring to the recommended operating conditions (main clock input oscillation fre-
________
quency) of the electric characteristics. However, when the user is using the RDY signal, the relevant
bit in the chip select control register’s bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each areas selected using the chip select signal. Bits 4 to 7 of the chip select control register corre-
_______ _______
spond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one
BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default
to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Also, insert a software wait if using the multiplex bus to access the external memory area.
Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.7 shows example bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the
protect register (address 000A16) to “1”.
Table 2.4.9 Software waits and bus cycles
Area
Bus status
Wait bit
Bits 4 to 7 of chip select
control register
SFR
Invalid
Invalid
Internal
0
ROM/RAM
1
Separate bus
0
Separate bus
0
External
memory
Separate bus
1
area
Multiplex bus
0
Multiplex bus
1
Note: When using the RDY signal, always set to “0”.
Invalid
Invalid
1
0
0 (Note)
0
0 (Note)
Bus cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
Rev. 1.0
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