M306H2MC-XXXFP Datasheet, PDF (101/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
UART2 special mode register 2 (I²C bus exclusive register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
When reset
0016
Bit
symbol
Bit name
Function
IICM2 I²C mode selection bit 2 Refer to Table 2.11.11
CSC Clock-synchronous bit
SWC SCL wait output bit
ALS
SDA output stop bit
STAC ^{UART2 initialization bit}
SWC2 SCL wait output bit 2
SDHI ^{SDA output disable bit}
SHTC Start/stop condition
control bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
Set this bit to "1" in I²C mode
(refer to Table 2.11.12)
RW
UART2 special mode register 3 (I²C bus exclusive register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
When reset
Indeterminate
(initializing value is "0016" at SDDS = "1")
Bit
symbol
Bit name
Function
(I²C bus exclusive)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
“0” is read out when SDDS = 1. (Note1)
DL0
DL1
SDA digital delay value
setting bit
(Note1, Note2, Note3,
Note4)
b7 b6 b5
0 0 0 : Analog delay
0 0 1 : 1–2 cycle of 1/f (Xin)(Digital delay)
0 1 0 : 2–3 cycle of 1/f (Xin)(Digital delay)
0 1 1 : 3–4 cycle of 1/f (Xin)(Digital delay)
1 0 0 : 4–5 cycle of 1/f (Xin)(Digital delay)
DL2
1 0 1 : 5–6 cycle of 1/f (Xin)(Digital delay)
1 1 0 : 6–7 cycle of 1/f (Xin)(Digital delay)
1 1 1 : 7–8 cycle of 1/f (Xin)(Digital delay)
Notes 1: Reading and writing is possible when bit7 (SDDS = SDA digital delay selection
bit) of UART2 special mode register (U2SMR/address 037716) is "1". When
set SDDS = "1" and read out initialized value of UART2 special mode register
3(U2SMR3), this value is "0016".When set SDDS = "1" and write to UART2
special mode register 3(U2SMR3), set "0" to bit 0 to bit 4. When SDDS = "0",
writing is enable. When read out, this value is indeterminate.
2: When SDDS = "0" , this bit is initialized and become "000", selected analog
delay circuit. This bit is become "000" after end reset released, and selected
analog delay circuit. Reading out is possible when only SDDS = "1". when
SDDS = "0", value which was read out is indeterminate.
3: Delaying ; Only analog delay value when analog delay is selected, and only
digital delay value when digital delay is selected.
4: Delay level depends on SCL pin and SDA pin. And, when use external clock,
delay is increase around 100ns. So test first, and use this.
RW
Figure 2.11.9 UARTi -related registers (6)
100
Rev. 1.0