M306H2MC-XXXFP Datasheet, PDF (197/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25^oC, CM15 = “1” unless
otherwise specified)
Table 4.24 In memory expansion and microprocessor modes (With wait, accessing external
memory, multiplex bus area selected)
Symbol
Parameter
Measuring condition
td(BCLK-AD) Address output delay time
th(BCLK-AD) Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
th(WR-AD) Address output hold time (WR standard)
td(BCLK-CS)
th(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
th(RD-CS)
Chip select output hold time (RD standard)
th(WR-CS) Chip select output hold time (WR standard)
td(BCLK-RD) RD signal output delay time
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Figure 4.1
td(DB-WR) Data output delay time (WR standard)
th(WR-DB) Data output hold time (WR standard)
td(BCLK-ALE) ALE signal output delay time (BCLK standard)
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
td(AD-ALE) ALE signal output delay time (Address standard)
th(ALE-AD) ALE signal output hold time (Adderss standard)
td(AD-RD)
Post-address RD signal output delay time
td(AD-WR) Post-address WR signal output delay time
tdZ(RD-AD) Address output floating start time
Note: Calculated according to the BCLK frequency as follows:
Standard
Min. Max.
40
4
(Note)
(Note)
40
4
(Note)
(Note)
40
0
40
0
40
4
(Note)
(Note)
40
–4
(Note)
50
0
0
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10⁹
th(RD – AD) =
f(BCLK) X 2
[ns]
th(WR – AD) =
10 ⁹
f(BCLK) X 2
[ns]
10 ⁹
th(RD – CS) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – CS) =
f(BCLK) X 2
[ns]
td(DB – WR) =
10 ⁹ X 3
– 40
f(BCLK) X 2
[ns]
10 ⁹
th(WR – DB) =
f(BCLK) X 2
[ns]
10 ⁹
td(AD – ALE) =
– 40
f(BCLK) X 2
[ns]
Rev. 1.0
196