M306H2MC-XXXFP Datasheet, PDF (100/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UCON
Address
03B016
When reset
X00000002
Bit
symbol
Bit name
U0IRS UART0 transmit
interrupt cause select bit
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
RW
U1IRS UART1 transmit
0 : Transmit buffer empty (Tl = 1)
interrupt cause select bit
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
Invalid
CLKMD0 CLK/CLKS select bit 0
CLKMD1 CLK/CLKS select bit
1 (Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Invalid
Must always be “0”
Reserved bit
Must always be “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
0016
Bit
symbol
Bit name
IICM I²C mode selection bit
Function
(During clock synchronous
serial I/O mode)
0 : Normal mode
1 : I²C mode
Function
(During UART mode)
Must always be “0”
RW
ABC ^{Arbitration lost detecting} 0 : Update per bit
flag control bit
1 : Update per byte
Must always be “0”
BBS Bus busy flag
0 : STOP condition detected
1 : START condition detected
Must always be “0”
(Note 1)
LSYN SCLL sync output
enable bit
ABSCS ^{Bus collision detect}
sampling
clock select bit
ACSE
Auto clear function
select bit of transmit
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
Must always be “0”
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
SDDS
Transmit start condition
select bit
SDA digital delay
selection bit
(Notes 2 and 3)
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
0 : Analog delay output
selection
Must always be “0”
1 : Digital delay output selection
Notes 1: Nothing but "0" may be written.
2: Do not write "1" except at I²C mode. Must always be “0” at normal mode.
Bit 7 to bit5 (DL2 to DL0 = SDA digital delay value setting bit) of UART2 special mode
register 3 (U2SMR3/address 037516) are initialized and become “000” when this bit is "0", analog
delay circuit is selected. Reading and writing U2SMR3 are enablewhen SDDS = "0".
3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value
when digital delay is selected.
Figure 2.11.8 UARTi I/O-related registers (5)
Rev. 1.0
99