M306H2MC-XXXFP Datasheet, PDF (150/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
The each head address of the address is corresponded to acquisition line has stored next acquisition information.
PDC
VPS
VBI
Other
SR00F to SR004
0
0
0
0
SR003
field * (Note)
field * (Note)
field * (Note)
0
SR002
0
0
1
0
SR001
0
1
0
0
SR000
1
0
0
0
Note : * the first field : 1
the second field : 0
(1) PDC
In case of the PDC data, 16 bits (2 data) are stored for the 1 address from the LSB side.
Clock run-in
+ flaming code
Data 1
Data 3
Data 5
Data 2
Data 4
Data 6
Data 40
Data 42
Data 39
Data 41
L
ML
M
S
SS
S
B
BB
B
SR010
SR01F
SR020
SR030
S02F
S03F SR140
S14F
SR150
S15F
SR16x to SR17x are unused area.
(2) VPS
In case of the VPS data, 8 bits (a data) are stored for an address from the LSB side.
Low-order 8 bits stores the acquisition data. And, high-order 8 bits become warning bit, when the send data is not recognized as
bi-phase type.
The case of bi-phase data ="1,0" or "0,1" (the bi-phase type) becomes "0" for this warning bit, and it becomes "1" in bi-phase data
="0,0" or "1,1" (it is not the bi-phase type). (For example, bi-phase data of SR011 is "0,0" or "1,1", "1" is set to SR019.)
Clock run-in
+ flaming code
Data 1
Data 3
Data 2
Data 4
Data 12
Data 11
Data 13
L
S
B
SR010
ML
M
SS
S
BB
B
SR017 ^{SR030 SR037}
SR0B0 SR0B7SR0D0 SR0D7
SR020 SR027 SR040 SR047
SR0C0
SR0C7
SR0Ex to SR17x are unused area.
(3) VBI
Clock run-in
+ flaming code
Data 1
Data 2
Data 3
Data 4
Data 5
L
ML
M
S
SS
S
B
BB
B
SR010
SR017
SR020
SR030
SR027
SR037
SR040
SR050
SR047
SR057
SR06x to SR17x are unused area.
Figure 2.15.2 Slice RAM bit composition
Rev. 1.0
149