M306H2MC-XXXFP Datasheet, PDF (115/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
RxDi
Start bit
Stop bit
D0
D1 D7
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
RTSi
Receive interrupt
request bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive register to
UARTi receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
Figure 2.11.19 Typical receive timing in UART mode
(1) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
(2) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 2.11.20 shows the ex-
ample of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
Transfer clock ^{“H”}
“L”
TxD2 ^{“H”}
(no reverse) _{“L”}
TxD2 ^“H”
(reverse) _{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST : Start bit
P : Even parity
SP : Stop bit
Figure 2.11.20 Timing for switching serial data logic
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Rev. 1.0