M306H2MC-XXXFP Datasheet, PDF (203/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
In memory expansion and microprocessor modes
(When Accessing External Memory Area With Wait, And Select Multiplexed bus)
Read timing
BCLK
CSi
td(BCLK–CS)
40ns.max
td(AD–ALE)
(tcyc/2-40)ns.min
ADi
/DBi
Address
tdz(RD–AD)
8ns.max
ADi
td(BCLK–AD)
40ns.max
tcyc
th(ALE–AD)
30ns.min
tac3(RD–DB)
td(AD–RD)
0ns.min
BHE
ALE
td(BCLK–ALE)
40ns.max
th(BCLK–ALE)
–4ns.min
td(BCLK–RD)
40ns.max
RD
th(RD–CS)
(tcyc/2)ns.min
th(BCLK–CS)
4ns.min
Data input
th(RD–DB)
tSU(DB–RD) 0ns.min
40ns.min
Address
th(BCLK–AD)
4ns.min
th(RD–AD)
(tcyc/2)ns.min
th(BCLK–RD)
0ns.min
Write timing
BCLK
CSi
td(BCLK–CS)
40ns.max
ADi
/DBi
ADi
BHE
ALE
Address
td(AD–ALE)
(tcyc/2–40)ns.min
td(BCLK–AD)
40ns.max
td(BCLK–ALE)
40ns.max
th(BCLK–ALE)
–4ns.min
WR,WRL,
WRH
tcyc
td(BCLK–DB)
40ns.max
th(WR–CS)
(tcyc/2)ns.min
Data output
th(BCLK–CS)
4ns.min
th(BCLK–DB)
4ns.min
Address
td(DB–WR)
(tcyc*3/2–40)ns.min
th(WR–DB)
(tcyc/2)ns.min
th(BCLK–AD)
4ns.min
td(AD–WR)
0ns.min
td(BCLK–WR)
40ns.max
th(WR–AD)
(tcyc/2)ns.min
th(BCLK–WR)
0ns.min
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
Figure 4.6 Timing diagram (5)
202
Rev. 1.0