M306H2MC-XXXFP Datasheet, PDF (47/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
2.7.5 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or
absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable
flag (I flag) and the IPL are located in the flag register (FLG).
Figure 2.7.3 shows the memory map of the interrupt control registers.
Rev. 1.0
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