M306H2MC-XXXFP Datasheet, PDF (52/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 2.7.5
Table 2.7.5 Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value 16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Notes 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Notes 2: Locate an interrupt vector address in an even address, if possible.
BCLK
Address bus
Data bus
R
W
12
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Address
0000
Interrupt
information
Indeterminate
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
SP-2
SP-4
vec
vec+2
contents contents contents contents
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 2.7.5 Time required for executing the interrupt sequence
(2) Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values
shown in Table 2.7.6 is set in the IPL.
Table 2.7.6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
Reset
Other
Value set in the IPL
7
0
Not changed
Rev. 1.0
51