M306H2MC-XXXFP Datasheet, PDF (196/210 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306H2MC-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
Switching characteristics (refer to VCC = 5V, VSS = 0V at Ta = 25^oC, CM15 = “1” unless otherwise
specified)
Table 4.23 In memory expansion and microprocessor modes (With wait, accessing external memory)
Symbol
Parameter
Measuring condition ^Standard
Min. Max.
Unit
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
40
ns
4
ns
0
ns
0
ns
td(BCLK-CS)
th(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
40
ns
4
ns
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
40
ns
–4
ns
Figure 4.1
40
ns
th(BCLK-RD) RD signal output hold time
0
ns
td(BCLK-WR)
th(BCLK-WR)
WR signal output delay time
WR signal output hold time
40
ns
0
ns
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
40
ns
4
ns
(Note1)
ns
th(WR-DB)
Data output hold time (WR standard)(Note2)
0
ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 ⁹
f(BCLK) ^{– 40} [ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
R
Hold time of data bus is expressed in
DBi
t = –CR X ln (1 – VOL / VCC)
C
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7µs.
Rev. 1.0
195