UM10360 Datasheet, PDF (824/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 35: LPC17xx Supplementary information
Chapter 15: LPC17xx UART1
1
Basic configuration . . . . . . . . . . . . . . . . . . . . 316
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 317
4
Register description . . . . . . . . . . . . . . . . . . . 318
4.1
UART1 Receiver Buffer Register (U1RBR -
0x4001 0000, when DLAB = 0). . . . . . . . . . . 319
4.2
UART1 Transmitter Holding Register (U1THR -
0x4001 0000 when DLAB = 0) . . . . . . . . . . . 319
4.3
UART1 Divisor Latch LSB and MSB Registers
(U1DLL - 0x4001 0000 and U1DLM -
0x4001 0004, when DLAB = 1). . . . . . . . . . . 319
4.4
UART1 Interrupt Enable Register (U1IER -
0x4001 0004, when DLAB = 0). . . . . . . . . . . 320
4.5
UART1 Interrupt Identification Register (U1IIR -
0x4001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 321
4.6
UART1 FIFO Control Register (U1FCR -
4.6.1
0x4001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 323
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 323
4.7
UART1 Line Control Register (U1LCR -
0x4001 000C) . . . . . . . . . . . . . . . . . . . . . . . . 324
4.8
UART1 Modem Control Register (U1MCR -
0x4001 0010) . . . . . . . . . . . . . . . . . . . . . . . . 324
4.9
Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 325
15.4.9.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
15.4.9.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Chapter 16: LPC17xx CAN1/2
1
Basic configuration . . . . . . . . . . . . . . . . . . . . 341
2
CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 341
3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
3.1
General CAN features . . . . . . . . . . . . . . . . . 341
3.2
CAN controller features . . . . . . . . . . . . . . . . 342
3.3
Acceptance filter features . . . . . . . . . . . . . . . 342
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 342
5
CAN controller architecture . . . . . . . . . . . . . 342
5.1
APB Interface Block (AIB) . . . . . . . . . . . . . . 343
5.2
Interface Management Logic (IML). . . . . . . . 343
5.3
Transmit Buffers (TXB) . . . . . . . . . . . . . . . . . 343
5.4
Receive Buffer (RXB) . . . . . . . . . . . . . . . . . 344
5.5
Error Management Logic (EML) . . . . . . . . . 345
5.6
Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . 345
5.7
Bit Stream Processor (BSP) . . . . . . . . . . . . . 345
5.8
CAN controller self-tests . . . . . . . . . . . . . . . . 345
6
Memory map of the CAN block. . . . . . . . . . . 347
7
CAN controller registers . . . . . . . . . . . . . . . . 347
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.16.1
4.17
4.18
4.19
4.20
4.21
4.22
5
UART1 Line Status Register (U1LSR -
0x4001 0014) . . . . . . . . . . . . . . . . . . . . . . . . 327
UART1 Modem Status Register (U1MSR -
0x4001 0018) . . . . . . . . . . . . . . . . . . . . . . . . 328
UART1 Scratch Pad Register (U1SCR -
0x4001 001C) . . . . . . . . . . . . . . . . . . . . . . . 329
UART1 Auto-baud Control Register (U1ACR -
0x4001 0020) . . . . . . . . . . . . . . . . . . . . . . . . 329
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 331
UART1 Fractional Divider Register (U1FDR -
0x4001 0028) . . . . . . . . . . . . . . . . . . . . . . . . 332
Baud rate calculation . . . . . . . . . . . . . . . . . . 333
UART1 Transmit Enable Register (U1TER -
0x4001 0030) . . . . . . . . . . . . . . . . . . . . . . . . 335
UART1 RS485 Control register (U1RS485CTRL -
0x4001 004C) . . . . . . . . . . . . . . . . . . . . . . . 336
UART1 RS-485 Address Match register
(U1RS485ADRMATCH - 0x4001 0050) . . . . 337
UART1 RS-485 Delay value register
(U1RS485DLY - 0x4001 0054) . . . . . . . . . . 337
RS-485/EIA-485 modes of operation . . . . . . 337
UART1 FIFO Level register (U1FIFOLVL -
0x4001 0058) . . . . . . . . . . . . . . . . . . . . . . . . 339
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 339
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.9.1
CAN Mode register (CAN1MOD - 0x4004 4000,
CAN2MOD - 0x4004 8000) . . . . . . . . . . . . . 349
CAN Command Register (CAN1CMR -
0x4004 x004, CAN2CMR - 0x4004 8004) . . 351
CAN Global Status Register (CAN1GSR -
0x4004 x008, CAN2GSR - 0x4004 8008) . . 352
CAN Interrupt and Capture Register (CAN1ICR -
0x4004 400C, CAN2ICR - 0x4004 800C) . . 355
CAN Interrupt Enable Register (CAN1IER -
0x4004 4010, CAN2IER - 0x4004 8010) . . . 358
CAN Bus Timing Register (CAN1BTR -
0x4004 4014, CAN2BTR - 0x4004 8014) . . 359
CAN Error Warning Limit register (CAN1EWL -
0x4004 4018, CAN2EWL - 0x4004 8018) . . 360
CAN Status Register (CAN1SR - 0x4004 401C,
CAN2SR - 0x4004 801C). . . . . . . . . . . . . . . 361
CAN Receive Frame Status register (CAN1RFS -
0x4004 4020, CAN2RFS - 0x4004 8020) . . 363
ID index field . . . . . . . . . . . . . . . . . . . . . . . . 363
continued >>
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
824 of 835