UM10360 Datasheet, PDF (576/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
Table 534: A/D Status register (AD0INTEN - address 0x4003 400C) bit description
Bit Symbol
Value Description
3
ADINTEN3 0
1
4
ADINTEN4 0
1
5
ADINTEN5 0
1
6
ADINTEN6 0
1
7
ADINTEN7 0
1
8
ADGINTEN 0
1
31:17 -
Completion of a conversion on ADC channel 3 will not generate an interrupt.
Completion of a conversion on ADC channel 3 will generate an interrupt.
Completion of a conversion on ADC channel 4 will not generate an interrupt.
Completion of a conversion on ADC channel 4 will generate an interrupt.
Completion of a conversion on ADC channel 5 will not generate an interrupt.
Completion of a conversion on ADC channel 5 will generate an interrupt.
Completion of a conversion on ADC channel 6 will not generate an interrupt.
Completion of a conversion on ADC channel 6 will generate an interrupt.
Completion of a conversion on ADC channel 7 will not generate an interrupt.
Completion of a conversion on ADC channel 7 will generate an interrupt.
Only the individual ADC channels enabled by ADINTEN7:0 will generate
interrupts.
Only the global DONE flag in ADDR is enabled to generate an interrupt.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Reset
value
0
0
0
0
0
1
NA
5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to
0x4003 402C)
The A/D Data Registers hold the result of the last conversion for each A/D channel, when
an A/D conversion is complete. They also include the flags that indicate when a
conversion has been completed and when a conversion overrun has occurred.
Results of ADC conversion can be read in one of two ways. One is to use the A/D Global
Data Register to read all data from the ADC. Another is to use the A/D Channel Data
Registers. It is important to use one method consistently because the DONE and
OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D
Channel Data Registers, potentially causing erroneous interrupts or DMA activity.
Table 535: A/D Data Registers (AD0DR0 to AD0DR7 - 0x4003 4010 to 0x4003 402C) bit description
Bit Symbol Description
Reset
value
3:0 -
Reserved, user software should not write ones to reserved bits. The value read from a
NA
reserved bit is not defined.
15:4 RESULT
29:16 -
When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] NA
pin, as it falls within the range of V_REFP to V_REFN. Zero in the field indicates that the voltage on
the input pin was less than, equal to, or close to that on V_REFN, while 0x3FF indicates that the
voltage on the input was close to, equal to, or greater than that on V_REFP.
Reserved, user software should not write ones to reserved bits. The value read from a
NA
reserved bit is not defined.
30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and
overwritten before the conversion that produced the result in the RESULT bits.This bit is
cleared by reading this register.
31 DONE
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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