UM10360 Datasheet, PDF (410/835 Pages) NXP Semiconductors – LPC17xx User manual

UM10360
Chapter 18: LPC17xx SSP0/1 interface
Rev. 01 — 4 January 2010
User manual
1. Basic configuration
The two SSP interfaces, SSP0 and SSP1 are configured using the following registers:
1. Power: In the PCONP register (Table 4–46), set bit PCSSP0 to enable SSP0 and bit
PCSSP1 to enable SSP1.
Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1).
2. Clock: In PCLKSEL0 select PCLK_SSP1; in PCLKSEL1 select PCLK_SSP0 (see
Section 4–7.3. In master mode, the clock must be scaled down (see Section 18–6.5).
3. Pins: Select the SSP pins through the PINSEL registers (Section 8–5) and pin modes
through the PINMODE registers (Section 8–4).
4. Interrupts: Interrupts are enabled in the SSP0IMSC register for SSP0 and SSP1IMSC
register for SSP1 Table 18–376. Interrupts are enabled in the NVIC using the
appropriate Interrupt Set Enable register, see Table 6–50.
5. Initialization: There are two control registers for each of the SSP ports to be
configured: SSP0CR0 and SSP0CR1 for SSP0, SSP1CR0 and SSP1CR1 for SSP1.
See Section 18–6.1 and Section 18–6.2.
6. DMA: The Rx and Tx FIFOs of the SSP interfaces can be connected to the GPDMA
controller (see Section 18–6.10). For GPDMA system connections, see
Table 31–544.
Remark: SSP0 is intended to be used as an alternative for the SPI interface, which is
included as a legacy peripheral. Only one of these peripherals can be used at the any one
time.
2. Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
• Synchronous Serial Communication.
• Master or slave operation.
• 8 frame FIFOs for both transmit and receive.
• 4 to 16 bit data frame.
• DMA transfers supported by GPDMA.
3. Description
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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