UM10360 Datasheet, PDF (400/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 17: LPC17xx SPI
4. Pin description
Table 359. SPI pin description
Pin Type Pin Description
Name
SCK
Input/
Output
Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of
data across the SPI interface. The SPI is always driven by the master and
received by the slave. The clock is programmable to be active high or active
low. The SPI is only active during a data transfer. Any other time, it is either in its
inactive state, or tri-stated.
SSEL Input
Slave Select. The SPI slave select signal (SSEL) is an active low signal that
indicates which slave is currently selected to participate in a data transfer. Each
slave has its own unique slave select signal input. The SSEL must be low before
data transactions begin and normally stays low for the duration of the
transaction. If the SSEL signal goes high any time during a data transfer, the
transfer is considered to be aborted. In this event, the slave returns to idle, and
any data that was received is thrown away. There are no other indications of this
exception. This signal is not directly driven by the master. It could be driven by a
simple general purpose I/O under software control.
MISO
Input/
Output
Master In Slave Out. The SPI Master In Slave Out signal (MISO) is a
unidirectional signal used to transfer serial data from an SPI slave to an SPI
master. When a device is a slave, serial data is output on this pin. When a
device is a master, serial data is input on this pin. When a slave device is not
selected, the slave drives the signal high-impedance.
MOSI
Input/
Output
Master Out Slave In. The SPI Master Out Slave In signal (MOSI) is a
unidirectional signal used to transfer serial data from an SPI master to an SPI
slave. When a device is a master, serial data is output on this pin. When a
device is a slave, serial data is input on this pin.
5. SPI data transfers
Figure 17–73 is a timing diagram that illustrates the four different data transfer formats
that are available with the SPI port. This timing diagram illustrates a single 8-bit data
transfer. The first thing you should notice in this timing diagram is that it is divided into
three horizontal parts. The first part describes the SCK and SSEL signals. The second
part describes the MOSI and MISO signals when the Clock Phase control bit (CPHA) in
the SPI Control Register is 0. The third part describes the MOSI and MISO signals when
the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with the
Clock Polarity control bit (CPOL) in the SPI Control Register set to both 0 and 1. The
second point to note is the activation and de-activation of the SSEL signal. When
CPHA = 0, the SSEL signal will always go inactive between data transfers. This is not
guaranteed when CPHA = 1 (the signal can remain active).
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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