UM10360 Datasheet, PDF (524/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 25: LPC17xx Motor Control PWM
Table 456. MCPWM Control read address (MCCON - 0x400B 8000) bit description
Bit
Symbol
Value Description
Reset
value
16
RUN2
Stops/starts timer channel 2.
0
0
Stop.
1
Run.
17
CENTER2
Edge/center aligned operation for channel 2.
0
0
Edge-aligned.
1
Center-aligned.
18
POLA2
Selects polarity of the MCOA2 and MCOB2 pins.
0
0
Passive state is LOW, active state is HIGH.
1
Passive state is HIGH, active state is LOW.
19
DTE2
Controls the dead-time feature for channel 1.
0
0
Dead-time disabled.
1
Dead-time enabled.
20
DISUP2
Enable/disable updates of functional registers for channel 2 (see Section 25–8.2). 0
0
Functional registers are updated from the write registers at the end of each PWM
cycle.
1
Functional registers remain the same as long as the timer is running.
28:21 -
-
Reserved.
29
INVBDC
Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set
to 1 only in 3-phase DC mode.
0
The MCOB outputs have opposite polarity from the MCOA outputs (aside from
dead time).
1
The MCOB outputs have the same basic polarity as the MCOA outputs. (see
Section 25–8.6)
30
ACMODE
3-phase AC mode select (see Section 25–8.7).
0
0
3-phase AC-mode off: Each PWM channel uses its own timer-counter and period
register.
1
3-phase AC-mode on: All PWM channels use the timer-counter and period register
of channel 0.
31
DCMODE
3-phase DC mode select (see Section 25–8.6).
0
0
3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)
1
3-phase DC mode on: The internal MCOA0 output is routed through the MCCP (i.e.
a mask) register to all six PWM outputs.
7.1.2 MCPWM Control set address (MCCON_SET - 0x400B 8004)
Writing ones to this write-only address sets the corresponding bits in MCCON.
Table 457. MCPWM Control set address (MCCON_SET - 0x400B 8004) bit description
Bit
Description
31:0 Writing ones to this address sets the corresponding bits in the MCCON register. See Table 25–456.
7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008)
Writing ones to this write-only address clears the corresponding bits in MCCON.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
524 of 835